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HI-8588
August 2006
ARINC 429 LINE RECEIVER
PIN CONFIGURATION
VCC - 1 TESTA - 2 RINB - 3 RINA - 4 8 - TESTB
DESCRIPTION
The HI-8588 is an ARINC 429 bus interface receiver and is available in a SO 8 pin package. The technology is analog/digital CMOS. The circuitry requires only a 5 volt supply. The ARINC bus can be connected directly to the chip. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold. The TESTA and TESTB inputs bypass the analog for testing purposes. Also if TESTA and TESTB are both taken high, the analog powers down and the digital outputs tristate allowing wire-or possibilities. Please refer to the HI-8588-10 for applications where an external resistance in series with the ARINC inputs is required for lightning protection or when the digital outputs need to be a logic zero rather than open circuit when TESTA and TESTB are both high. See Holt Application Note AN-300 for more information on lightning protection.
8588PS
7 - ROUTB 6 - ROUTA 5 - GND
8 - PIN PLASTIC NARROW BODY SOIC
SUPPLY VOLTAGES
vcc = 5.0V 5%
FUNCTION TABLE
RECEIVER
RINA -1.25V to 1.25V -3.25V to -6.5V RINB -1.25V to 1.25V 3.25V to 6.5V -3.25V to -6.5V X X X TESTA 0 0 0 0 1 1 TESTB 0 0 0 1 0 1 ROUTA ROUTB 0 0 1 0 1 HI-Z 0 1 0 1 0 HI-Z
FEATURES
3.25V to 6.5V X
! ! ! ! !
Direct ARINC 429 line receiver interface in a small outline package Receiver input hystersis at least 2 volts Test inputs that bypass analog input and can power down and tri-state outputs Plastic and ceramic package options surface mount and DIP Mil processing available
X X
PIN DESCRIPTION TABLE
PIN 1 2 3 4 5 6 7 8 SYMBOL VCC TESTA RINB RINA GND ROUTA ROUTB TESTB FUNCTION SUPPLY LOGIC INPUT ARINC INPUT ARINC INPUT POWER LOGIC OUTPUT LOGIC OUTPUT LOGIC INPUT CMOS RECEIVER B INPUT RECEIVER A INPUT GROUND RECEIVER CMOS OUTPUT A RECEIVER CMOS OUTPUT B CMOS DESCRIPTION 5 VOLT SUPPLY
(DS8588 Rev. C)
HOLT INTEGRATED CIRCUITS www.holtic.com
08/06
HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER Figure 1 shows the general architecture of the ARINC 429 receiver. The receiver operates off the VCC supply only. The inputs RINA and RINB each have series resistors, typically 35K ohms. They connect to level translators whose resistance to Ground is typically 10K ohms. Therefore, any series resistance added to the inputs will affect the voltage translation. After level translation, the inputs are buffered and become inputs to a differential amplifier. The amplitude of the differential signal is compared to levels derived from a divider between VCC and Ground. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of the TESTA and TESTB pins. If TESTA and TESTB are both One, then the receiver is powered down and the output pins float. The powerdown does not disconnect the internal resistors at the ARINC input.
ONE
S Q LATCH R
TEST
ROUTA TEST TESTA
TESTA ' TESTB
RINA
RINB
ESD PROTECTION AND TRANSLATION
NULL TEST
ZERO
S Q LATCH R
ROUTB
TEST TESTB
TESTA ' TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
5V
1
HARDWIRE OR DRIVE FROM LOGIC
{
2 8 4
VCC
TESTA TESTB
ROUTA ROUTB
6 7
RXD1 RXD0
HI-8588
RINA RINB
APPLICATION INFORMATION
Figure 2 shows a possible application of the HI-8588 interfacing an ARINC receive channel to the HI-6010 which in turn interfaces to an 8-bit bus.
ARINC Channel
3
HI-6010
5
15V
1 6
SLP1.5 TXAOUT V+ TX1IN
8 BIT BUS
8 3 2
TXD1
ARINC Channel
7
HI-8586
TXBOUT GND VTX0IN
TXD0
4
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS 2
HI-8588 ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground Supply voltages VCC...................................................7V ARINC input - pins 3 & 4 Voltage at either pin......+29V to -29V DC current per input pin................ 10mA Power dissipation at 25C plastic DIP............0.7W ceramic DIP..........0.5W Solder Temperature ........275C for 10 sec Storage Temperature........-65C to +150C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. Supply Voltages VCC...........................................5V 5% Temperature Range Industrial Screening........-40C to +85C Hi-Temp Screening.......-55C to +125C Military Screening.........-55C to +125C
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED PARAMETERS ARINC input voltage one or zero null common mode logic input voltage high low ARINC input resistance RINA to RINB RINA or RINB to Gnd or VCC logic input current source sink logic output drive current one zero Current drain operating powerdown SYMBOL V DIN VNIN VCOM V IH V IL R DIFF R SUP I IH I IL I OH I OL I CC1 I CC2 supplies floating " " TEST CONDITIONS differential voltage, pins 3 & 4 " " " with respect to Ground MIN 6.5 TYP 10 MAX 13 2.5 5.0 UNITS volts volts volts
3.5 -
-
1.5
volts volts
30 19
75 40
-
Kohm Kohm
V IN = 0 V V IN = 5 V V = 4.6V OH V = 0.4V OL pins 2, 8 = 0V; pins 3, 4 open pins 2, 8 = 5V; pins 3, 4 open
-
-
0.1 0.1
A A
3.6
-1.6 5.6
-0.8 -
mA mA
-
2.3 0.36
6.3 0.6
mA mA
HOLT INTEGRATED CIRCUITS 3
HI-8588 AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED PARAMETERS Receiver propagation delay Output high to low Output low to high Receiver output transition times Output high to low Output low to high Input capacitance (1) ARINC differential ARINC single ended to Ground Logic
Notes: 1. Guaranteed but not tested
SYMBOL TEST CONDITIONS defined in Figure 3, C L= 50pF t phlr t plhr t fr t rr CAD CAS C IN
MIN
TYP
MAX
UNITS
-
600 600
-
ns ns
-
50 50 5 -
80 80 10 10 10
ns ns pF pF pF
VDIFF pin 4 - pin 3
t plhr t phlr
90%
10V
0V
-10V
t rr
pin 6
t plhr
10%
5V 0V
t fr
t phlr
pin 7
FIGURE 3 - RECEIVER TIMING
5V 0V
ORDERING INFORMATION
HI - 8588 xx x x
PART NUMBER LEAD FINISH
Blank F
PART NUMBER
Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE RANGE FLOW BURN IN
I T M
PART NUMBER
-40C TO +85C -55C TO +125C -55C TO +125C
PACKAGE DESCRIPTION
I T M
NO NO YES
PD PS CR
8 PIN PLASTIC DIP (not available with "M" flow) 8 PIN PLASTIC NARROW BODY SOIC 8 PIN CERDIP (not available Pb-free)
HOLT INTEGRATED CIRCUITS 4
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN PLASTIC DIP
Package Type: 8P
.385 .015 (4.699 .381)
.250 .010 (6.350 .254) .100 .010 (3.540 .254) .300 .010 (7.620 .254) 7 TYP. .135 .015 (3.429 .381) .1375 .0125 (3.493 .318) .019 .002 (.483 .102) .025 .010 (.635 .254) .0115 .0035 (.292 .089) .055 .010 (1.397 .254) .335 .035 (8.509 .889)
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB (Narrow Body)
.1935 .0035 (4.915 .085)
Package Type: 8HN
.0086 .0012 (.2184 .0305) .236 .008 (5.994 .203)
PIN 1
.1535 .0035 (3.90 .09)
.0165 .0035 (.4191 .0889)
Detail A
.055 .005 (1.397 .127)
0 to 8
.050 .010 (1.27 .254) .033 .017 (.8382 .4318)
.0069 .0029 (.1753 .0737)
Detail A
HOLT INTEGRATED CIRCUITS 5
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN CERDIP
Package Type: 8D
.380 .004 (9.652 .102) .005 MIN. (.127 MIN.) .248 .003 (6.299 .076) .039 .006 (.991 .154)
.100 .008 (2.540 .203) .015 MIN. (.381 MIN.)
.314 .003 (7.976 .076)
.200 MAX. (5.080 MAX.) .163 .037 (4.140 .940)
Base Plane Seating Plane
.056 .006 (1.422 .152) .018 .006 (.457 .152) .350 .030 (8.890 .762)
.010 .006 (.254 .152)
HOLT INTEGRATED CIRCUITS 6

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